Memory is a part of every CPU design and SoC. Integrated memories have timing requirements to be met just as any mega-module. These timing parameters are dictated by the address/data decoders, the bit cells and the latches; that vary with the type of memory.
These timing parameters include setup time and hold time on the input interface and the clk-to-output delay. These timing parameters have a significant bearing on the maximum achievable frequency of the design. Placement and routing tools rely on timing parameters given by liberty files. Thus the characterization and validation of these numbers are crucial. The spice characterization data has to be validated on silicon by actual measurement of these parameters. Memory testchips have test circuits meant for timing characterization.
The problem is to design a circuit to characterize these timing parameters for the memory:
1. Setup/Hold for Address bus;
2. Setup/Hold for Data bus;
3. Clk to Q delay.
The circuit should be self-contained requiring minimal user intervention and be capable of characterizing all bit-lines in the bus.
FIG. 1 illustrates a block diagram of a prior art characterization circuit 100. Characterization circuit 100 includes circuit under test 110, signal generator 120 and oscilliscope 130. Signal generator 120 generates test signals. These are applied to the inputs of memory 115 via multiplexers 111 and 113 in an appropriate sequence. Oscilloscope 130 receives outputs from memory 115 and the test signals from signal generator 120. Thus user of characterization circuit 100 observes the response of memory 115 on the display of oscilloscope 130.
In this prior art circuit, measurement was based on oscilloscope observations. Characterization circuit 110 required differential signaling and had tight constraints on the physical design. Characterization circuit 110 does not measure the parameters directly. The user must make measurements via oscilloscope 130 outside the circuit under test 100.